Dynamic address translation (DAT) is a function in data processing systems that allows programmers to write programs using virtual or logical addresses, leaving it to a supervisor or control program to store data and programs in real, physical, main memory of a system, and translate the virtual addresses to the real addresses in main memory. This function is found in mainframes of The International Business Machines Corporation, and had a beginning in the IBM System/370 architecture. Enhancements have been made to the function through the System/390, and present ESA/390 architecture.
The following patents, all assigned to the assignee of the present application, describe the use of DAT with the present access register translation (ART) mechanism now defined as part of the ESA/390 architecture. These patents are herewith incorporated by reference to describe these existing functions for which the present invention is a further enhancement:
1. U.S. Pat. No. 4,695,950 entitled "Fast Two-level Dynamic Address Translation Method and Means" by Brandt et al describes the use of segment tables and page tables used as part of the DAT process;
2. U.S. Pat. No. 4,500,952 entitled "Mechanism For Control Of Address Translation By A Program Using A Plurality Of Translation Tables" by Heller et al enhances the DAT process in the previous patent by allowing a program to use more than one set of segment and page tables, namely a primary set and a secondary set.
3. U.S. Pat. No. 4,979,098 entitled "Multiple Address Space Token Designation, Protection Controls, Designation Translation and Lookaside" by Baum et al describes the addition of access registers (AR) for each general purpose register that enter into an access register translation (ART) process for use in designating one of many (more than two as in previous patent) sets of segment and page tables to be used in the DAT process.
The current state of the art, using DAT, allows the execution of computer instructions with either DAT-on or DAT-off. With DAT-on, all computer instructions are available, but essentially all instruction operands must be expressed using virtual addresses. With DAT-off, all instruction operands are expressed as real, physical main store or central storage addresses. This is true when being used with a system that is also operating with access register translation (ART) also active.
MVS/ESA is an operating system, or control program, that manages a system under the ESA/390 architecture. The majority of function and services of MVS/ESA are available and supported only with DAT-on, and since DAT typically provides addressability of virtual storage far in excess of real storage, it is normally highly desirable for programs to execute with DAT-on, including programs comprising the basic operating system control program. There exists instances where programs must access central storage addresses with real and not virtual address. The current state of the art requires that programs with such requirements either perform costly and severely constraining mode switches between the DAT-on and DAT-off execution states, or use an extremely limited set of DAT-on instructions to manipulate only 4 bytes of central storage per instruction.
Additionally, because of the existing difficulties in central storage addressing with DAT-on, some basic control program components implement complex schemes for management of architecture and operating system constructs. For example, virtual storage translation structures, such as segment and page tables, can be managed themselves in virtual storage, but at the complicating expense of managing translation structures for the translation structures. And in turn, if the second level of translation structures are also managed in virtual storage, a third level of translation structures is required to address the second level.
Furthermore, there currently exists no general ESA/390 or MVS/ESA capability to concurrently address central storage and virtual storage addresses. There are several occasions within the course of basic control program execution where such a capability would provide significant potential for path reduction and simplification of program implementation.